1. Field of the Invention
The present invention relates to a memory device, and more specifically, it relates to a memory device storing data.
2. Description of the Background Art
A ferroelectric memory storing data through polarization of a ferroelectric substance is known in general. This ferroelectric memory is watched with interest as a high-speed nonvolatile memory requiring low power consumption. Therefore, the ferroelectric memory is actively researched and developed. A storage capacitance ferroelectric memory writing/reading data in a system similar to that of a DRAM (dynamic random access memory) employs one of two types of representative memory cells, i.e., a one-transistor two-capacitor (hereinafter referred to as 1T1C) memory cell and a two-transistor two-capacitor (hereinafter referred to as 2T2C) memory cell. The 2T2C memory cell is disclosed in xe2x80x9cLow-power High-speed LSI Circuits and Technologyxe2x80x9d, Jan. 31, 1998, pp. 235-245, for example.
FIG. 36 is a circuit diagram showing a memory cell part of a conventional 1T1C ferroelectric memory. FIG. 37 is a circuit diagram for illustrating a method of reading data in the conventional 1T1C ferroelectric memory including memory cells and reference cells.
As shown in FIG. 36, each memory cell 103 of the conventional 1T1C ferroelectric memory is formed by a selection transistor 101 and a ferroelectric capacitor 102, similarly to that of a DRAM. When the selection transistor 101 is turned on in a reading operation of the ferroelectric memory, the ferroelectric capacitor 102 is connected with a bit line capacitor Cbl. Then, a plate line PL is pulse-driven to transmit charges varying with the direction of polarization of the ferroelectric capacitor 102 to a bit line BLT. Thus, the ferroelectric memory reads data as the voltage of the bit line BLT, similarly to the DRAM. Whether the data is xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d depends on the direction of polarization of the ferroelectric capacitor 102. In this case, a reference cell is required for discharging charges in an intermediate quantity between those of charges discharged by the data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d in data reading.
More specifically, reference cells 103a are connected to a pair of bit lines BLT and BLB respectively, as shown in FIG. 37. The data read operation is now described in detail with reference to FIG. 37. First, the pair of bit lines BLT and BLB are precharged to 0 V. When a word line WL1 selects a memory cell 103 connected with the bit line BLT, a word line RefWLB selects the reference cell 103a connected with the bit line BLB. When a word line WL2 selects a memory cell 103 connected with the bit line BLB, a word line RefWLT selects the reference cell 103a connected with the bit line BLT. Thereafter the plate line PL is pulse-driven so that charges corresponding to the memory cells 103 and the reference cells 103a are discharged to the pair of bit lines BLT and BLB. Thus, the pair of bit lines BLT and BLB obtain data signals of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. A sense amplifier 105 amplifies the difference between the potentials of the signals. Thus, the ferroelectric memory reads data.
FIG. 38 is a circuit diagram showing a memory cell part of a conventional 2T2C ferroelectric memory. As shown in FIG. 38, two transistors and two capacitors are connected to a pair of bit lines BLT and BLB in the memory cell part of the 2T2C ferroelectric memory. The two transistors and the two capacitors store complementary data as 1-bit data. In this case, no reference cells are required for preparing reference voltages for reading the complementary data, dissimilarly to the aforementioned 1T1C ferroelectric memory.
In general, a matrix storage capacitance ferroelectric memory is also proposed. FIG. 39 is a circuit diagram showing memory cells 121 of a conventional matrix ferroelectric memory. As shown in FIG. 39, ferroelectric capacitors 122 are arranged on intersections between word lines WL1 to WL4 and bit lines BL1 to BL4 in the memory cells 121 of the conventional matrix ferroelectric memory. The matrix ferroelectric memory, reading voltages through capacitive coupling between the bit lines BL1 to BL4 and the ferroelectric capacitors 122, must ensure the capacitance similarly to the 1T1C ferroelectric memory. In the matrix ferroelectric memory, each memory cell 121 is formed by only a single ferroelectric capacitor 122, whereby the degree of integration can be more improved as compared with the 1T1C ferroelectric memory.
FIG. 40 is a schematic diagram for illustrating the operation principle of the matrix ferroelectric memory shown in FIG. 39. Operations of the conventional matrix ferroelectric memory are now described with reference to FIGS. 39 and 40.
First, each ferroelectric capacitor 122 has first and second ends connected to each word line WL and each bit line BL respectively. Both ends of the ferroelectric capacitor 122 are at the same potential in a standby state. In order to write data xe2x80x9c1xe2x80x9d, voltages of Vcc and 0 V are applied to the word line WL and the bit line BL respectively. At this time, the voltage Vcc is applied to the ferroelectric capacitor 122. Thus, the ferroelectric capacitor 122 shifts to a point A in FIG. 40 despite an initial state. When both ends of the ferroelectric capacitor 122 are thereafter set to the same potential, the ferroelectric capacitor 122 makes transition to xe2x80x9c1xe2x80x9d in FIG. 40. In order to write data xe2x80x9c0xe2x80x9d, voltages of 0 V and Vcc are applied to the word line WL and the bit line BL respectively. At this time, a voltage xe2x88x92Vcc is applied to the ferroelectric capacitor 122. Thus, the ferroelectric capacitor 122 shifts to a point B in FIG. 40. When both ends of the ferroelectric capacitor 122 are thereafter set to the same potential, the ferroelectric capacitor 122 makes transition to xe2x80x9c0xe2x80x9d in FIG. 40.
In a read operation, the bit line BL is precharged to 0 V. Then, the word line WL is set to the voltage Vcc. Assuming that Ccell represents the capacitance of the ferroelectric capacitor 122 of each memory cell, Cref represents the capacitance of a ferroelectric capacitor 122a of each reference cell 121a (see FIG. 39), Cbl represents the parasitic capacitance of a bit line BLn and Cblref represents the parasitic capacitance of a reference bit line Blref, the voltage Vcc of the word line WL is capacitively divided by the capacitances Ccell and Cbl as to the bit line BLn, and capacitively divided by the parasitic capacitances Cref and Cblref as to the reference bit line Blref. The capacitance Ccell can be approximated as a capacitance C0 or C1 depending on held data. Therefore, a potential V0 of the bit line BLn holding data xe2x80x9c0xe2x80x9d, a potential V1 of the bit line BLn holding the data xe2x80x9c1xe2x80x9d and a potential Vref of the reference bit line Blref are expressed as follows respectively:
V0={C0 /(C0+Cbl)}xc3x97Vccxe2x80x83xe2x80x83(1)
V1={C1/(C1+Cbl)}xc3x97Vccxe2x80x83xe2x80x83(2)
Vref={(Cref/(Cref+Cblref))xc3x97Vccxe2x80x83xe2x80x83(3)
The potential Vref of the reference bit line Blref is set to an intermediate level between the potential V0 of the bit line BLn holding the data xe2x80x9c0xe2x80x9d and the potential V1 of the bit line BLn holding the data xe2x80x9c1xe2x80x9d.
A sense amplifier determines the difference between the potential V0 or V1 and the potential Vref thereby performing reading. At this time, data of the memory cell is destroyed and hence a write operation (restoration) responsive to the read data is performed after the reading.
The conventional 1T1C ferroelectric memory shown in FIG. 36 having the memory cells each formed by only a single transistor and a single capacitor advantageously has a high degree of integration. However, a reference voltage disadvantageously deviates from a design value due to fabrication dispersion of the ferroelectric capacitor 102 of change of the quantity of polarization charges in the write and read operations or resulting from time change. This disadvantageously leads to false data reading.
In the conventional 2T2C ferroelectric memory shown in FIG. 38, each memory cell is formed by two ferroelectric capacitors and two selection transistors, and hence the degree of integration is inferior to that of the 1T1C ferroelectric memory.
In the conventional matrix ferroelectric memory shown in FIG. 39, false data reading disadvantageously results from fabrication dispersion or fluctuation of a reference voltage caused by change of the quantity of polarization charges. Further, the matrix ferroelectric memory disadvantageously causes a disturbance phenomenon of a non-selected cell in the write and read operations. In the matrix ferroelectric memory, a voltage of xc2xd Vcc is regularly applied to a non-selected bit line BL and a non-selected word line WL and hence the voltage of xc2xd Vcc is applied to the non-selected cell at the maximum. As shown in FIG. 41, therefore, disturbance is repeated due to hysteretic characteristics of a ferroelectric substance to reduce the quantity of polarization charges. When the quantity of polarization charges is reduced, that of each reference cell 122a is also reduced, to result in remarkable fluctuation of the aforementioned reference voltage. This disadvantageously further prompts false data reading.
An object of the present invention is to provide a memory device capable of improving the degree of integration and effectively preventing false reading.
Another object of the present invention is to effectively prevent a non-selected memory cell from a disturbance phenomenon in the aforementioned memory device.
A memory device according to an aspect of the present invention comprises a pair of bit lines extending in a prescribed direction, a word line arranged to intersect with the pair of bit lines and a memory cell, arranged between the pair of bit lines and the word line, consisting of two capacitance means.
The memory device according to this aspect is provided with the memory cell consisting of two capacitance means as described above, whereby the area of the memory cell can be reduced as compared with a conventional memory cell consisting of two capacitance means and two transistors and hence the degree of integration can be improved. When complementary data are written in the two capacitance means respectively, no reference voltage is required and initial potential difference in reading can be increased as compared with a case of employing the reference voltage. Thus, false data reading can be effectively prevented also when the characteristics of the capacitance means are deteriorated due to fabrication dispersion or increase of the number of write/read times.
In the memory device according to the aforementioned aspect, the capacitance means preferably include a ferroelectric layer. According to this structure, the ferroelectric memory can be formed in a high degree of integration to be capable of effectively preventing false data reading.
In the memory device according to the aforementioned aspect, the two capacitance means preferably store complementary data respectively, thereby storing one-bit data in the memory cell. According to this structure, no reference voltage is required and initial potential difference in reading can be increased.
In this case, the memory device preferably applies a pulsing voltage to a selected word line while applying complementary voltages to a selected pair of bit lines when writing the data. According to this structure, the memory device can write first data in a first bit line in a high-level voltage period of a pulse while writing second data in a second bit line in a low-level voltage period of the pulse. Consequently, the memory device can write complementary data in the pair of bit lines in a cycle of one pulse.
The memory device applying the aforementioned pulsing voltage preferably further comprises a pulse voltage application circuit for applying the pulsing voltage to the selected word line at least when writing the data. According to this structure, the memory device can easily apply the pulsing voltage to the selected word line.
The memory device applying the aforementioned pulsing voltage preferably further comprises a write voltage application circuit for applying the complementary voltages to the selected pair of bit lines when writing the data. According to this structure, the memory device can easily apply the complementary voltages to the selected pair of bit lines.
The memory device applying the aforementioned pulsing voltage may apply a prescribed voltage to a selected memory cell while applying a voltage substantially half the prescribed voltage to a non-selected memory cell when writing and reading data.
The memory device applying the aforementioned pulsing voltage reads the data by detecting difference between the potentials of the pair of bit lines corresponding to the complementary data stored in the two capacitance means respectively. According to this structure, the memory device can easily read the data.
In this case, the memory device preferably detects the difference between the potentials of the pair of bit lines corresponding to the complementary data stored in the two capacitance means respectively by precharging the pair of bit lines connected with the selected memory cell to a prescribed voltage and thereafter applying the pulsing voltage to the word line connected with the selected memory cell when reading the data. According to this structure, the memory device can easily detect the difference between the potentials of the pair of bit lines in a high-voltage period of the pulsing voltage.
In this case, the memory device preferably further comprises a read amplifier for amplifying the difference between the potentials of the pair of bit lines corresponding to the complementary data stored in the two capacitance means respectively. According to this structure, the memory device can easily read the data.
The memory device according to the aforementioned aspect preferably applies a prescribed voltage to a selected memory cell while applying a voltage of substantially one third of the prescribed voltage to a non-selected memory cell when writing and reading data. According to this structure, the non-selected memory cell can be effectively prevented from a disturbance phenomenon.
In this case, the memory device may apply the prescribed voltage to a selected memory cell connected with the first one of the pair of bit lines while applying the voltage of substantially one third of the prescribed voltage to the non-selected memory cell and a selected memory cell connected with the second one of the pair of bit lines thereby writing prescribed data in the selected memory cell connected with the first one of the pair of bit lines and thereafter applying the prescribed voltage to the selected memory cell connected with the second one of the pair of bit lines while applying the voltage of substantially one third of the prescribed voltage to the non-selected memory cell and the selected memory cell connected with the first one of the pair of bit lines thereby writing data inverse to the prescribed data in the selected memory cell connected with the second one of the pair of bit lines when writing the data. According to this structure, the memory device can write the data while reducing the voltage applied to the non-selected cell to substantially one third of the prescribed voltage.
In this case, the memory device detects the difference between the potentials of the pair of bit lines corresponding to the complementary data stored in the two capacitance means respectively by precharging the pair of bit lines connected with the selected memory cell to a prescribed first voltage and thereafter applying a prescribed second voltage to the word line connected with the selected memory cell when reading the data. According to this structure, the memory device can read the data while reducing the voltage applied to the non-selected cell to substantially one third of the prescribed voltage.
The memory device according to the aforementioned aspect is preferably capable of applying a pulse having a prescribed pulse width causing polarization inversion when a high voltage is applied to the capacitance means while causing substantially no polarization inversion when a low voltage is applied to the capacitance means to the memory cell, for applying a pulse of a high voltage having the prescribed pulse width to a selected memory cell while applying a pulse of a low voltage having the prescribed pulse width to a non-selected memory cell at least either in data writing or in data reading. According to this structure, the memory device can write or read data in or from the selected memory cell while causing substantially no polarization inversion in the non-selected memory cell by applying a pulse of a high voltage having the aforementioned prescribed pulse width to the selected memory cell and applying a pulse of a low voltage having the aforementioned prescribed pulse width to the non-selected memory cell at least either in data writing or in data reading. Consequently, the non-selected memory cell can be prevented from disturbance. In this case, the prescribed pulse width is preferably not more than 70 ns.
In the memory device according to the aforementioned aspect, at least either the bit lines forming the pair of bit lines or the word line has a multilevel structure, and the capacitance means preferably have multilevel structures. When the capacitance means formed between the bit lines and the word line have multilevel structures, the degree of integration can be improved as compared with a case of employing capacitance means having single-level structures.
In the memory device including the aforementioned capacitance means having multilevel structures, the two capacitance means forming each memory cell may include a first data storage part and a second data storage part storing complementary data respectively, and the first data storage part and the second data storage part may be transversely arranged at a prescribed interval. According to this structure, the memory cell including the first and second data storage parts can be vertically stacked, whereby the degree of integration can be improved.
In the memory device including the aforementioned capacitance means having multilevel structures, the two capacitance means forming each memory cell may include a first data storage part and a second data storage part storing complementary data respectively, and the first data storage part and the second data storage part may be vertically arranged at a prescribed interval. According to this structure, the first and second data storage parts forming the memory cell can be vertically stacked, whereby the degree of integration can be improved.
In the memory device including the aforementioned capacitance means having multilevel structures, the two capacitance means forming each memory cell may include a first data storage part and a second data storage part storing complementary data respectively, and the first data storage part and the second data storage part may be obliquely arranged at a prescribed interval. According to this structure, the first and second data storage parts forming the memory cell can be obliquely stacked, whereby the degree of integration can be improved.
In the memory device including the aforementioned capacitance means having multilevel structures, the bit lines forming the pair of bit lines are preferably arranged above and under the word line respectively, and the capacitance means preferably include a first data storage layer arranged between the bit line located above the word line and the word line and a second data storage layer arranged between the bit line located under the word line and the word line. According to this structure, the capacitance means (data storage layers) can have two-level structures, whereby the degree of integration can be improved as compared with a case of employing capacitance means of single-level structures.
In the memory device including the capacitance means having the aforementioned multilevel structures, the bit lines forming the pair of bit lines preferably include at least first- and second-level bit lines, the word line preferably includes at least first- and second-level word lines, and the capacitance means preferably include a first data storage layer arranged between the first-level bit line and the first-level word line and a second data storage layer arranged between the second-level bit line and the second-level word line, while the memory device preferably further comprises an insulator layer formed between a first region formed with the first data storage layer, the first-level word line and the first-level bit line and a second region formed with the second data storage layer, the second-level word line and the second-level bit line for isolating the first region and the second region from each other. According to this structure, ferroelectric capacitors vertically adjacent to each other can be isolated from each other.
In the memory device including the capacitance means having the aforementioned multilevel structures, the bit lines forming the pair of bit lines preferably include at least first-, second- and third-level bit lines, the word line preferably includes at least first- and second-level word lines, and the capacitance means preferably include a first data storage layer arranged between the first-level bit line and the first-level word line, a second data storage layer arranged between the first-level word line and the second-level bit line, a third data storage layer arranged between the second-level bit line and the second-level word line and a fourth data storage layer arranged between the second-level word line and the third-level bit line. According to this structure, memory cells vertically adjacent to each other can share the second-level bit line, whereby the number of interconnection layers (bit lines and word lines) can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.